This Course is mainly focuses on FinFet layout design techniques used in the physical design of standard cells, Memory layout design and full custom digital and analog blocks. Starting with the FinFet layouting of basic MOS transistors to industry standard project execution in FinFet technologies, the course develops to cover the more advanced techniques used in creating area efficient full custom digital & analog layouts.

Eligibility
B.E/B.Tech/Diploma in ECE/EEE.
M.E/M.Tech/M.S in VLSI System Design/Embedded Systems/Digital Electronics.
1-3 Years Experienced Analog Layout Design Working Professionals.